1. Field of the Invention
The present invention generally relates to gate array circuits and, more particularly, the present invention relates to large semi-custom integrated circuits that have large gate arrays and large routing channels.
2. State of the Art
It is well known to use standardized gate arrays to construct semi-custom integrated circuits. An example of a typical semiconductor integrated circuit or "chip" 15 based upon gate arrays is shown in FIG. 1 and is described in U.S. Pat. No. 4,562,453. In this example, the chip 15 has four peripheral blocks 11, 12, 13 and 14 that surround four internal functional gate regions 21, 22, 23 and 24. The spaces between the internal functional gate regions comprise routing channels or "tracks" 31, 32 and 33, for routing wires.
In a gate array chip of the type shown in FIG. 1, the peripheral blocks normally are used for input/output functions such as signal level conversion. In the internal functional gate regions, logic gates are regularly arrayed so that various circuits, herein referred to as "macro cells," can be constructed. The macro cells are interconnected by wiring that passes through the routing tracks 31, 32 and 33.
FIG. 2A shows a conventional layout of an internal functional gate region or "gate array base" of a gate array chip. More particularly, the drawing depicts a high-density CMOS gate array wherein rows of P-type transistors alternate with rows of N-type transistors. (In the following discussion, a P-type transistor row and an N-type transistor row are together referred to as a placement row.) The transistors are formed in pairs by extending polysilicon gate lines (e.g., line 47) across P-type or N-type diffusion regions (e.g., region 49). A macro cell might be placed, for instance, in the dark outlined region 53 of the gate array base. A typical macro cell is one placement row high and as many rows wide as necessary to realize its required function.
Further in the conventional layout gate array base shown in FIG. 2A, every "pair of pairs" --that is, every four transistors--is flanked on either side by a substrate connection region (e.g., 51).
FIG. 2B shows a typical example of an AND gate laid out in a macro cell according to the prior art, with the macro cell being a single placement row (i.e., two transistor rows) high. As indicated by the annotations to the drawing, the AND gate is realized from a two input NAND gate--having inputs A1 and A2, and output X--which is connected in series with an inverter to produce an output Z. That is, the left-hand side of the macro cell realizes the NAND gate function and the right-hand side realizes the inverter function.
In FIG. 2B, the solid shading represents polysilicon (e.g., region 37), the cross-hatching represents metal (e.g., region 39), and the large dotted-outline rectangular areas (e.g., region 41) represent diffusion regions. The diffusion regions in the upper half of the macro cell are of the P type, with polysilicon crossing twice above each diffusion region to form four P-type transistors. In the upper left-hand quadrant, the two P-type transistors are connected in parallel by the metal layer so that the transistors share a common output.
In the lower half of the macro cell in FIG. 2B, the diffusion regions are of the N-type with polysilicon crossing twice above each diffusion region to form four N-type transistors. More particularly, in the lower left-hand quadrant, two N-type transistors are connected in series with their output being taken to the right of the gate line farthest to the right. The gates of one of the P-type and one of the N-type transistors are joined together to form an input A1 and the gates of the other P-type and other N-type transistor are Joined together to form an input A2. The outputs of the parallel P-type combination and the series N-type combination are connected in common by metal to form the output X of the NAND gate.
As also shown in FIG. 2B, the macro cell includes contacts between metal and diffusion or polysilicon, represented by square outlines (e.g., region 40). The contacts between metal and a hidden metal layer are represented by a darkened square (e.g., region 43) located in substrate connected regions (e.g., region 45) between the basic cells.
When inputs A1 and A2 are both high during operation of the macro cell of FIG. 2B, the P-type transistors are both in the "off" state and the series-connected N-type transistors are both in the "on" state. This configuration results in a low voltage V.sub.SS being passed to the output of the second N-type transistor, thereby causing the output to go low. When either inputs A1 or A2 is low, at least one of the parallel-connected P-type transistors is "on," with the result that a high voltage V.sub.DD is passed through to the common output of the P-type transistors to cause the output to go high. At the same time, at least one of series-connected N-type transistors is off, with the result that the low voltage V.sub.SS is not passed through to the output.
On the inverter side of the macro cell of FIG. 2B, the output of the NAND gate is connected in common to each of the gates of the two P-type and two N-type transistors. When output X is at voltage V.sub.SS, the P-type transistors are turned on and, as a result, the high voltage V.sub.DD is passed through to the output Z and the two N-type transistors are turned off. When output X is high at V.sub.DD, the N-type transistors are turned on, with the result that the low voltage V.sub.SS is passed through to the output Z and the two P-type transistors are turned off.
One limitation of conventional gate arrays is that the routing area cannot be readily increased. One suggested way to this shortcoming is to run routing channels parallel to the transistors, thereby forming a column macro cell. This solution, however, constrains the macro cell sizes to be of fixed width and of a height that is a multiple of a large number of routing tracks (for example, eight). Thus, in this suggested solution, flexibility in routing channel size was gained at the expense of reduced flexibility in sizing macro cells.
Another suggested solution to the above-described shortcoming was to use field isolation (instead of gate isolation) and to separate P-type and N-type transistor gates. With the gates separated, a routing channel can be as small as either the N-type or P-type transistors. With the P-type and N-type gates connected according to the gate isolation technique, by contrast, a routing channel must be as high as the sum of the heights of the P-type and N-type transistors.
Even in field isolated designs, however, the commonly-used routing channel size has been approximately the same as the height of one P-type and N-type transistor. For large gate arrays, the resulting routing channel size is not large enough if the transistors are small. If the transistors are made larger, the routing channel size is less adjustable, since the minimum increment is the height of a P-type or N-type transistor. Large transistors also have larger gate capacitances, a disadvantage in many circuits.
A further problem encounted in the prior art is the obstruction of potential routing tracks by a known power grid arrangement shown in FIGS. 5 and 6. FIG. 5 shows a portion of the power grid formed in a first metalization layer (metal1), and FIG. 6 shows in addition the portion of the power grid formed in a second metalization layer (metal2). Referring first to FIG. 5, metal1 busses 61 are formed horizontally through the middle of each transistor row. The busses 61 cross the gate electrodes of all the transistors and also cross well-tie diffusion regions 65 formed at four transistor intervals along each transistor row. Conventionally, wherever one of the metal1 busses 61 crosses a well-tie diffusion region 65, a contact is formed between the bus and the diffusion region for purposes to be explained presently in connection with FIG. 6.
Referring now to FIG. 6, opposite types of transistors are formed in alternate transistor rows by for example forming P+ diffusion regions 62 in n- wells 66 to form P-type transistors and by forming N+ diffusion regions 64 in P- wells 68 to form N-type transistors. Where adjacent n- and P-wells adjoin, parasitic diodes 67 are formed that, if allowed to enter a conductive state, may cause circuit latch-up. Well-tie diffusion regions 65 are provided to ensure that the parasitic diodes 67 are always reverse biased. For example, in the n-wells 66, the well-tie region 65 are formed of n+ diffusion (to minimize voltage drop across the well-tie diffusion region) and tied to voltage V.sub.DD supplied by one of the metal1 busses 61. In the P-wells 68, well-tie regions 65 are formed of P+ diffusion and are tied to voltage V.sub.SS (ground) supplied by one of the metal1 busses 61. As a result, the parasitic diodes 67 are always reverse biased.
To complete the power grid, metal2 straps 63 are formed vertically and connected by vias to metal1 busses 61 supplying the same voltage. Complications arise, however, because vias and contacts are not allowed to occupy the same area on the chip (i.e., vias and contacts cannot be formed on top of one another). Moreover, what would otherwise be the preferred locations for vias connecting the metal2 straps 63 to the metal1 busses 61 are already occupied by contacts C connecting the metal1 busses 61 to the well-tie diffusions 65. As a result, in the prior art, vertical stubs have been extended from the metal1 busses 61 underlying the metal2 strap 63, so as to allow vias to be placed as necessary in the locations V1 spaced apart vertically from the contacts C. Also, the metal2 straps 63 have been made wider than (twice as wide as) the metal1 busses 61, allowing vias to be placed as necessary in the locations V2.
The disadvantage of such a technique is that routing tracks are obstructed. A grid of dots superimposed on the field of FIG. 6 (and also FIGS. 5 and 7) indicates potential routing tracks. If a via is placed at any of the locations V1, a potential horizontal routing track in the metal1 layer is obstructed. If a via is placed at any of the locations V2, a potential vertical routing track in the metal2 layer is obstructed. This situation limits the placement of macros that require use of these routing tracks.